1. Field of the Invention
The present invention relates to a circuit which allows adjustment of the delay of a logic signal by means of a control signal.
2. Discussion of the Related Art
Analog phase shifters are often used as adjustable delay circuits due to their ease of adjustment. However, when such a phase shifter is used with logic signals, it has the drawback of reducing the slopes and the amplitude of the logic signals, due to its limited band-width. Thus, a phase shifter cannot be used for adjusting the delay of high frequency logic signals, unless it has an unreasonably high band-width.
Analog delay lines have the same drawbacks as phase shifters.
In digital delay lines, the input signal is sampled, and the samples are stored so that they can be provided subsequently with the desired delay. For the delay to be accurate enough, the sampling frequency should be much higher than the frequency of the input signal. This precludes the use of digital delay lines for high frequency logic signals.
In a so-called quasi-linear delay circuit, a capacitor is alternately charged and discharged at a constant current as the input signal switches from one state to the other. The delayed signal results from a comparison of the voltage across the capacitor with a threshold.
However, such a circuit can only be used when the input signal has a constant duty ratio of 50%, otherwise the voltage across the capacitor would diverge.